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ics for consumer electronics controller for switch mode power supplies supporting low power standby and power factor correction tda 16846/tda 16847 data sheet 2000-01-14
tda 16846/tda 16847 revision history: current version: 2000-01-14 previous version: 1999-07-05 page (in previous version) page (in current version) subjects (major changes since last revision) 3 3, 28 p-dso package added edition 01.00 published by infineon technologies ag i. gr., st.-martin-strasse 53 d-81541 mnchen ? infineon technologies ag 2000 all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, des criptions and charts stated herein. infineon technologiesis an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologi es office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infin eon tech- nologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system , or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet 3 2000-01-14 controller for switch mode power supplies supporting low power standby and power factor correction tda 16846 tda 16847 preliminary data bipolar ic p-dso-14-3 p-dip-14-3 1 overview 1.1 features ? line current consumption with pfc ? low power consumption ? stable and adjustable standby frequency ? very low start-up current ? soft-start for quiet start-up ? free usable fault comparators ? synchronization and fixed frequency facility ? over- and undervoltage lockout ? switch off at mains undervoltage ? temporary high power circuit (only tda 16847) ? mains voltage dependent fold back point correction ? continuous frequency reduction with decreasing load ? adjustable and voltage dependent ringing suppression time 1.2 description the tda 16846 is optimized to control free running or fixed frequency flyback converters with or without power factor correction (current pump). to provide low power consumption at light loads, this device reduces the switching frequency continuously with load, towards an adjustable minimum (e. g. 20 khz in standby mode). additionally, the start up current is very low. to avoid switching stresses of the power devices, the power transistor is always switched on at minimum voltage. a special circuit is implemented to avoid jitter. the device has several protection functions: v cc over- and undervoltage, mains undervoltage, current limiting and 2 free usable fault comparators. regulation can be done by using the internal error amplifier or an opto coupler feedback (additional input). the output driver is ideally suited for driving a power mosfet, but it can also be used for a bipolar transistor. fixed frequency and synchronized operation are also possible. type ordering code package tda 16846 q67000-a9377 p-dip-14-3 tda 16847 q67000-a9378 p-dip-14-3 tda 16846g q67006-a9430 p-dso-14-3 tda 16847g q67006-a9412 p-dso-14-3
tda 16846 tda 16847 data sheet 4 2000-01-14 the tda 16846 is suited for tv-, vcr- sets and sat receivers. it also can be good used in pc monitors. the tda 16847 is identical with tda 16846 but has an additional power measurement output (pin 8) which can be used for a temporary high power circuit. figure 1 pin configuration (top view) 1.3 pin definitions and functions pin symbol function 1 otc off time circuit 2 pcs primary current simulation 3 rzi regulation and zero crossing input 4 src soft-start and regulation capacitor 5 oci opto coupler input 6 fc2 fault comparator 2 7 syn synchronization input 8 n.c./pmo not connected (tda 16846)/pmo (tda 16847) 9 ref reference voltage and current 10 fc1 fault comparator 1 11 pvc primary voltage check 12 gnd ground 13 out output 14 vcc supply voltage 10 8 9 1 2 3 4 5 6 14 7 13 12 otc 11 pcs rzi src oci fc2 syn n.c./pmo ref fc1 pvc gnd out aep02647 vcc
tda 16846 tda 16847 data sheet 5 2000-01-14 1.4 short description of the pin functions pin function 1 a parallel rc-circuit between this pin and ground determines the ringing suppression time and the standby-frequency. 2 a capacitor between this pin and ground and a resistor between this pin and the positive terminal of the primary elcap quantifies the max. possible output power of the smps. 3 this is the input of the error amplifier and the zero crossing input. the output of a voltage divider between the control winding and ground is connected to this input. if the pulses at pin 3 exceed a 5 v threshold, the control voltage at pin 4 is lowered. 4 this is the pin for the control voltage. a capacitor has to be connected between this pin and ground. the value of this capacitor determines the duration of the softstart and the speed of the control. 5 if an opto coupler for the control is used, its output has to be connected between this pin and ground. the voltage divider at pin 3 has then to be changed, so that the pulses at pin 3 are below 5 v. 6 fault comparator 2: if a voltage > 1.2 v is applied to this pin, the smps stops. 7 if fixed frequency mode is wanted, a parallel rc circuit has to be connected between this pin and ground. the rc-value determines the frequency. if synchronized mode is wanted, sync pulses have to be fed into this pin. 8 not connected (tda 16846). / this is the power measurement output of the temporary high power circuit. a capacitor and a rc-circuit has to be connected between this pin and ground (tda 16847). 9 output for reference voltage (5 v). with a resistor between this pin and ground the fault comparator 2 (pin 6) is enabled. 10 fault comparator 1: if a voltage > 1 v is applied to this pin, the smps stops. 11 this is the input of the primary voltage check. the voltage at the anode of the primary elcap has to be fed to this pin via a voltage divider. if the voltage of this pin falls below 1 v, the smps is switched off. a second function of this pin is the primary voltage dependent fold back point correction (only active in free running mode). 12 common ground. 13 output signal. this pin has to be connected across a serial resistor with the gate of the power transistor. 14 connection for supply voltage and startup capacitor. after startup the supply voltage is produced by the control winding of the transformer and rectified by an external diode.
tda 16846 tda 16847 data sheet 6 2000-01-14 1.5 block diagrams figure 2 tda 16846 aeb02648 - + + - 4 r d4 r 7 5 v 30 k w r 8 75 k w r 3 15 k w control voltage ksy + - pva 1.5 v 6 r 6 r d5 fold back point correction 1 v + - voltage check - + cc v 1.2 v 1 & off time comparator 2 v limit g1 3.5 v - + d2 error amplifier r 2 5 v d3 control voltage - + buffer for 5 v - + comparator overvoltage 1 r 20 k w < 25 mv 1.5 v i ed1 16 v comparator - + on time d1 startup g4 1 q s r ed2 error- flipflop on time flipflop r s q g2 voltage comparator - + 15/8 v zero crossing signal & output driver primary + - fc1 1 v 7 1 syn otc rzi 3 4 src 5 oci pcs 2 14 gnd 12 cc v 10 fc1 13 out 6 fc2 ref 9 n.c. 8 11 pvc x 1/3 1 diode supply the input with the lower voltage becomes operative 1) fc2 + g3 cs1 rstc/rstf 3.5 v - +
tda 16846 tda 16847 data sheet 7 2000-01-14 figure 3 tda 16847 aeb02737 - + + - 4 r d4 r 7 5 v 30 k w r 8 75 k w r 3 15 k w control voltage ksy + - pva 1.5 v 6 r 6 r d5 fold back point correction 1 v + - voltage check - + cc v 1.2 v 1 & off time comparator 2 v limit g1 3.5 v - + d2 error amplifier r 2 5 v d3 control voltage - + buffer for 5 v - + comparator overvoltage 1 r 20 k w < 25 mv 1.5 v i ed1 16 v comparator - + on time d1 startup g4 1 q s r ed2 error- flipflop on time flipflop r s q g2 supply voltage comparator - + 15/8 v crossing signal & output driver primary + - fc1 1 v 7 1 syn otc rzi 3 4 src 5 oci pcs 2 14 gnd 12 cc v 10 fc1 13 out 6 fc2 ref 9 pmo 8 11 pvc x 1/3 1 diode the input with the lower voltage becomes operative 1) fc2 + g3 cs1 rstc/rstf 3.5 v - + s1 s2 zero q r flipflop discharge time s 1)
tda 16846 tda 16847 data sheet 8 2000-01-14 2 functional description start up behaviour (pin 14) when power is applied to the chip and the voltage v 14 at pin 14 ( v cc ) is less than the upper threshold ( v on ) of the supply voltage comparator (svc), input current i 14 will be less than 100 m a. the chip is not active and driver output (pin 13) and control output (pin 4) will be actively held low. when v 14 exceeds the upper svc threshold ( v on ) the chip starts working and i 14 increases. when v 14 falls below the lower svc threshold ( v off ) the chip starts again at his initial condition. figure 4 shows the start-up circuit and figure 5 shows the voltage v 14 during start up. charging of c 14 is done by resistor r 2 of the primary current simulation (see later) and the internal diode d1, so no additional start up resistor is needed. the capacitor c 14 delivers the supply current until the auxiliary winding of the transformer supplies the chip with current through the external diode d14. figure 4 startup circuit aes02649 svc tda 16846 d1 2 14 cc v pcs 2 c r 2 c 14 c p out v tr d14
tda 16846 tda 16847 data sheet 9 2000-01-14 figure 5 startup voltage diagram primary current simulation pcs (pin 2) / current limiting a voltage proportional to the current of the power transistor is generated at pin 2 by the rc-combination r 2 , c 2 ( figure 4 ). the voltage at pin 2 is forced to 1.5 v when the power transistor is switched off and during its switch on time c 2 is charged by r 2 from the rectified mains. the relation of v 2 and the current in the power transistor ( i primary ) is : l primary : primary inductance of the transformer the voltage v 2 is applied to one input of the on time comparator ontc (see figure 2 ). the other input is the control voltage. if v 2 exceeds the control voltage, the driver switches off (current limiting). the maximum value of the control voltage is the internal reference voltage 5 v, so the maximum current in the power transistor ( i mprimary ) is : the control voltage can be reduced by either the error amplifier ea (current mode regulation), or by an opto coupler at pin 5 (regulation with opto coupler isolation) or by the voltage v 11 at pin 11 (fold back point correction). aed02650 t startup operation 14 v v max on v v off v 2 1,5 v l primary i primary r 2 c 2 ------------------------------- - + = i mprimary 3,5 v r 2 c 2 l primary -------------------------------------- =
tda 16846 tda 16847 data sheet 10 2000-01-14 fold back point correction pvc (pin 11) v 11 is deviated by a voltage divider from the rectified mains and reduces the limit of the possible current maximum in the power transistor if the mains voltage increases. i.e. this limit is independent of the mains (only active in free running mode). the maximum current ( i mprimary ) depending on the voltage v 11 at pin 11 is : off-time circuit otc (pin 1) figure 6 shows the off-time circuit which determines the load dependent frequency course. when the driver switches off ( figure 7 ) the capacitor c 1 is charged by current i 1 (approx. 1 ma) until the capacitors voltage reaches 3.5 v. the charge time tc1 is : for proper operation of the special internal anti jitter circuit, tc1 should have the same value as the resonance time tr of the power circuit ( figure 7 ). after charging c 1 up to 3.5 v the current source is disconnected and c 1 is discharged by resistor r 1 . the voltage v 1 at pin 1 is applied to the off-time comparator (oftc). the other input of oftc is the control voltage. the value of the control voltage at the input of oftc is limited to a minimum of 2 v (for stable frequency at very light load). the on-time flip flop (ontf) is set, if the output of oftc is high 1) and the voltage v 3 at pin 3 falls below 25 mv (zero crossing signal is high). this ensures switching on of the power transistor at minimum voltage. if no zero crossing signal is coming into pin 3, the power transistor is switched on after an additional delay until v 1 falls below 1.5 v (see figure 6 , oftcd). as long as v 1 is higher than the limited control voltage, ontf is disabled to suppress wrong zero crossings of v 3 , due to parasitic oscillations from the transformer after switch-off. the discharge time of c 1 is a function of the control voltage. 1) i.e. v 1 is less than the limited control voltage. . if the control voltage is below 2 v (at low output power) the off-time is maximum and constant control voltage output power off-time td1 1.5 - 2 v low constant (td1 max. ), const. frequency stand by 2 - 3.5 v medium decreasing 3.5 - 5 v high free running, switch-on at first minimum i mprimary 4v v 11 3 C () r 2 c 2 l primary ------------------------------------------------------------ = tc1 c 1 1,5 v 1ma ------------------------- ? td1 max 0,47 r 1 c 1 ?
tda 16846 tda 16847 data sheet 11 2000-01-14 figure 6 off-time-circuit aes02651 1 - + oftc & ed3 limit 2 v control voltage ed2 2 v s q r ontf & output driver from sync from ontc from uvlo rstc s r q ringing suppression time ed1 - + rstc zero crossing signal 1 i 3.5 v internal external 1 rc 1 1 otc from error ff rzi 3 oftcd + - 1.5 v 1
tda 16846 tda 16847 data sheet 12 2000-01-14 figure 7 pulse diagram of off-time-circuit figure 8 shows the converters switching frequency as a function of the output power. figure 8 load dependant frequency course aed02652 t 0 v 2 v 3.5 v 3 v v 13 v drain trans. power v 5 1 v c1 tt d1max t r aed02653 f out conventional free running tda 16846 e.g. 20 khz p
tda 16846 tda 16847 data sheet 13 2000-01-14 error amplifier ea / soft-start (pin 3, pin 4) figure 9 shows the simplified error amplifier circuit. the positive input of the error amplifier (ea) is the reference voltage 5 v. the negative input is the pulsed output voltage from the auxiliary winding, divided by r 31 and r 32 . the capacitor c 3 is dimensioned only for delaying zero crossings and smoothing the first spike after switch- off. smoothing of the regulation voltage is done with the soft start capacitor c 4 at pin 4. during start up c 4 is charged with a current of approx. 2 m a (soft start). figure 10 shows the voltage diagrams of the error amplifier circuit. figure 9 error amplifier figure 10 regulation pulse diagram aes02654 - + amplifier 5 v down 3 4 reg v tr 4 c 3 c internal external 31 r 32 r rzi src error aed02655 t ref v 3 v v 4 down
tda 16846 tda 16847 data sheet 14 2000-01-14 fixed frequency and synchronization circuit syn (pin 7) figure 11 shows the fixed frequency and synchronization circuit. the circuit is disabled when pin 7 is not connected. with r 7 and c 7 at pin 7 the circuit is working. c 7 is charged fast by approx. 1 ma and discharged slowly by r 7 ( figure 11 ). the power transistor is switched on at beginning of the charge phase. the switching frequency is (charge time ignored) : when the oscillator circuit is working the fold back point correction is disabled (not necessary in fixed frequency mode). switch on is only possible when a zero crossing has occurred at pin 3, otherwise switch-on will be delayed ( figure 12 ). figure 11 synchronization and fixed frequency circuit f 1,18 r 7 c 7 -------------- ? aes02656 - + 15 k w 75 k w 5 v 7 r c 7 syn 7 logic out rzi 13 3 zero crossing signal external internal 30 op1out op1 k w lo
tda 16846 tda 16847 data sheet 15 2000-01-14 figure 12 pulse diagram for fixed frequency circuit synchronization mode is also possible. the synchronization frequency must be higher than the oscillator frequency. figure 13 ext. synchronization circuit aed02657 t 0.7 v rzi(3) 1.5 v 3.6 v v trans v 7 v aes02658 5 v 470 w sfh 6136 7 r 39 k w 7 c 1 nf 9 7 internal external syn
tda 16846 tda 16847 data sheet 16 2000-01-14 3 protection functions the chip has several protection functions: current limiting see primary current simulation pcs (pin 2) / current limiting and fold back point correction pvc (pin 11). over- and undervoltage lockout ov/svc (pin 14) when v 14 at pin 14 exceeds 16 v, e. g. due to a fault in the regulation circuit, the error flip flop err is set and the output driver is shut-down. when v 14 goes below the lower svc threshold, err is reset and the driver output (pin 13) and the soft-start (pin 4) are shut down and actively held low. primary voltage check pvc (pin 11) when the voltage v 11 at pin 11 goes below 1 v the error flip flop (err) is set. e.g. a voltage divider from the rectified mains at pin 11 prevents from high input currents at too low input voltage. free usable fault comparator fc1 (pin 10) when the voltage at pin 10 exceeds 1 v, the error flip flop (err) is set. this can be used e. g. for mains overvoltage shutdown. free usable fault comparator fc2 (pin 6) when the voltage at pin 6 exceeds 1.2 v, the error flip flop (err) is set. a resistor between pin 9 (ref) and ground is necessary to enable this fault comparator. voltage dependent ringing suppression time during start-up and short-circuit operation, the output voltage of the converter is low and parasitic zero crossings are applied for a longer time at pin 3. therefore the ringing suppression time tc1 (see off-time circuit otc (pin 1)) is made longer with factor 2.5 at low output voltage. to ensure start-up of the circuit, the value of resistor r 1 (pin 1, figure 6 ) must be higher than 20 k w .
tda 16846 tda 16847 data sheet 17 2000-01-14 4 temporary high power circuit fc2, pmo, ref (pin 6, 8, 9, tda 16847) figure 14 shows the temporary high power circuit: figure 14 the temporary high power circuit (thpc) consists of two parts: first a power measurement circuit is implemented: the capacitor c 8 at pin 8 is charged with a constant current i 8 during the discharge time of the flyback transformer and connected to ground the other time. so the average of the sawtooth voltage v 8 at pin 8 is proportional to the converters output power (at constant output voltages). the charge current i 8 for c 8 is dimensioned by the resistor r 9 at pin 9: i 8 =5v/ r 9 - + 1.2 v 1 6 fc2 ref 9 8 fc2 s2 to error flipflop discharge time cs2 cc v 51 k r 9 w 8 c c 6 8 r pmo 6 10 m r w internal external aeb02739 i 8
tda 16846 tda 16847 data sheet 18 2000-01-14 second a high power shutdown comparator (fc2) is implemented: when the voltage v 6 at pin 6 exceeds 1.2 v the error flip flop (err) is set. the output voltage of the power measurement circuit (pin 8) is smoothed by r 8 / c 6 and applied to the high power shutdown input at pin 6. the relation between this voltage v 6 and the output power of the converter p is approximately: v 6 ? ( p l secondary 5 v)/( v out 2 c 8 r 9 ) l secondary : the transformers secondary inductance v out : the converters output voltage so the time constant of r 9 / c 8 for a certain high power shutdown level p sd is: r 9 c 8 ? ( p sd l secondary 4.2)/ v out 2 the converters high power shutdown level can be dimensioned lower (by r 9 , c 8 ) than the current limit level (see current limiting). so because of the delay r 8 / c 6 , the converter can deliver maximum output power (current limit level) for a certain time (e. g. for power pulses like motor start current) and a power below the high power shutdown level for unlimited time. this has the advantage that the thermal dimensioning of the power devices is only needed for the lower power level. once the voltage v 6 exceeds 1.2 v there are no more charge or discharge actions at pin 8. the voltage v 6 remains high due to the bias current out of hpc and the converter remains switched-off. reset can be done by either plug-off the supply from the mains or with a high value resistor r 6 ( figure 14 ). r 6 causes a reset every view seconds. when pin 9 is not connected or gets too less current the temporary high power circuit is disabled.
tda 16846 tda 16847 data sheet 19 2000-01-14 5 electrical characteristics note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5.1 absolute maximum ratings all voltages listed are referenced to ground (0 v, v ss ) except where noted. parameter symbol limit values unit remarks min. max. supply voltage at pin 14 v cc C0.3 17 v C voltage at pin 1, 4, 5, 6, 7, 9, 10 C C 0.3 6 v C voltage at pin 2, 8, 11 C C 0.3 17 v C voltage at pin 3 current into pin 3 rzi C10 6v ma v 3 < C 0.3 v current into pin 9 ref C 1 C ma C current into pin 13 out C 100 100 ma ma v 13 > v cc v 13 < 0 v esd protection C C 2 kv mil std 883c method 3015.6, 100 pf, 1500 w storage temperature t stg C 65 125 cC operating junction temperature t j C 25 125 cC thermal resistance junction-ambient r thja C 110 k/w p-dip-14-3 soldering temperature C C 260 cC soldering time C C 10 s C
tda 16846 tda 16847 data sheet 20 2000-01-14 5.2 characteristics unless otherwise stated, C25 c< t j < 125 c, v cc =12v parameter symbol limit values unit test condition min. typ. max. start-up circuit supply current, off i 14 C40100 m a0 < v cc < v 14 on supply current, on i 14 C 5 8 ma output low turn-on threshold v 14 on 14.5 15 15.5 v C turn-off threshold v 14 off 7.5 8 8.5 v C primary current simulation pcs (pin 2) / current limiting basic value v 2 1.45 1.5 1.55 v i 2 = 100 m a peak value v 2 4.85 5 5.15 v v 11 = 1.2 v on-time C 9.0 10.5 11.5 m s v 11 = 1.2 v, c 2 =220pf, i 2 = 75 m a bias current pin 2 C C 1.0 C 0.3 C m aC fold back point correction pvc (pin 11) peak value v 2 3.8 4.1 4.3 v v 11 = 4.5 v on-time C 6.2 7.5 8.5 m s v 11 = 4.5 v, c 2 =220pf, i 2 = 75 m a bias current pin 11 C C 1.0 C 0.3 C m aC off-time circuit otc (pin 1) charge current i 1 0.9 1.1 1.4 ma v 3 > 3 v charge current i 1 0.35 0.5 0.65 ma v 3 <2v peak value v 1 3.38 3.5 3.62 v C basic value v 1 1.92 2 2.08 v C
tda 16846 tda 16847 data sheet 21 2000-01-14 t12 charge time tc1 0.85 1.0 1.3 m s v 3 > 3 v, c 1 = 680 pf, r 1 = 100 k w t13 charge time tc1 1.9 2.4 3.0 m s v 3 < 2 v, c 1 = 680 pf, r 1 = 100 k w off-time td1 max. 65 72 80 m s c 1 = 680 pf, r 1 =100k w bias current pin 1 C C 1.1 C 0.4 C m aC zero crossing threshold (pin 3) C 152535mvC delay to switch-on C 280 350 480 ns C bias current pin 3 C C 2 C 1.2 C m a v 3 < 25 mv error amplifier ea (pin 3, pin 4) input threshold (pin 3) v eath 4.85 5 5.15 v C bias current pin 3 C C C 0.9 C m a v 3 > 3 v soft-start charge current (pin 4) C C 2.5 C 1.8 C 1.2 m aC opto coupler input (pin 5) input voltage range v 5 0.3 C 6 v C pull high resistor to v ref r 1 15 20 25 k w C 5.2 characteristics (contd) unless otherwise stated, C25 c< t j <125 c, v cc =12v parameter symbol limit values unit test condition min. typ. max.
tda 16846 tda 16847 data sheet 22 2000-01-14 fixed frequency and synchronization circuit syn (pin 7) frequency C788898khz c 7 = 470 pf, r 7 =20k w charge current i 7 1.0 1.3 1.6 ma C upper threshold v 7 3.5 3.6 3.7 v C lower threshold v 7 1.43 1.5 1.57 v C charge time C 0.4 0.55 0.75 m sC bias current pin 7 C C 2.4 C 1.8 C 1.1 m aC input voltage range v 7 0.3 C 6 v C undervoltage lockout svc (pin 14) threshold v 14 off 7.5 8 8.5 v C overvoltage lockout ov (pin 14) threshold v 14 ov 15.716.517 v C delta-ov- v 14 on C0.5CCvC primary voltage check pvc (pin 11) threshold v 11 0.95 1 1.06 v C reference voltage (pin 9) voltage at pin 9 v 9 4.8 5 5.15 v i 9 =100 m a current into pin 9 i 9 C200 C 0 m a v eath(pin 3) C v 9 <50mv 5.2 characteristics (contd) unless otherwise stated, C25 c< t j < 125 c, v cc =12v parameter symbol limit values unit test condition min. typ. max.
tda 16846 tda 16847 data sheet 23 2000-01-14 note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. fault comparator fc2 (pin 6) hpc threshold v 6 1.12 1.2 1.28 v C bias current pin 6 C C 1.0 C 0.3 0.1 m aC fault comparator fc1 (pin 10) threshold v 10 0.95 1 1.06 v C bias current pin 10 C 0.48 0.9 1.2 m aC power measurement output pmo (pin 8, only tda 16847) charge current pin 8 i 8 C110 C100 C90 m a i 9 =C100 m a output driver od (pin 13) output voltage low state v 13 low 1.1 1.8 2.4 v i 13 = 100 ma output voltage high state v 13 high 9.2 10 11 v i 13 = C 100 ma output voltage during low supply voltage v 13 aclow 0.8 1.8 2.5 v i 13 = C 10 ma, v 14 increasing: 0 < v 14 < v 14 on v 14 decreasing: 0< v 14 < v 14 off rise time C 70 110 180 ns c 13 = 10 nf, v 13 =28v fall time C 305080ns c 13 = 10 nf, v 13 =28v 5.2 characteristics (contd) unless otherwise stated, C25 c< t j <125 c, v cc =12v parameter symbol limit values unit test condition min. typ. max.
tda 16846 tda 16847 data sheet 24 2000-01-14 figure 15 circuit diagram for application with pfc aes02659 25 c 10 nf 4 r 24 18 k w 11 1 nf 24 c 23 r 3.9 m w 1 m r w 22 560 pf 22 c 2 5 3 29 r w 9.1 k 2 k p 10 w 6, 10, 12 c 22 150 pf 56 k r 30 w 1.5 nf 30 c 8 n.c. 9.1 k w 38 r m 220 f c 41 tr1 (al = 190 nh) d41 mur4100 52 turns 7 turns 1 v 100 v mur120 9 turns d42 f 470 m v 16 v 42 c 2 mur120 5 turns d43 8.5 v m v 470 43 c 3 f m 22 26 c f 1n4148 d26 13 7 9 r 35 w 15 mur4100 d9 c 9 220 pf 8 l 2 mh c 10 nf 8 stta506d d8 m 7 150 c f/450 v 4.7 m w 10 r w r 5 5.1 k 1 nf c 5 d1-d4 4 x byw 76 1 nf c 10 rfi filter 180-270 v 3.15 a f1 tda 16846 ic1 14 1 t1 54 turns c 28 4.7 nf 3 4 2 1 62 r 820 w 61 r 1 k w 61 10 nf c 1 nf 62 c 63 r 100 k w 2.2 k 60 r w p 500 w 60 w 65 100 k r ic 02 sfh 617 a-2 spp ( 0.6 w ) n6055
tda 16846 tda 16847 data sheet 25 2000-01-14 figure 16 circuit diagram for standard application aes02660 25 c 10 nf 4 r 24 18 k w 11 1 nf 24 c 23 r 3.9 m w 1 m r w 22 680 pf 22 c 2 5 3 29 r w 9.1 k 2 k p 10 w 6, 10, 12 c 22 150 pf 56 k r 30 w 1.5 nf 30 c 8 n.c. 9.1 k w 38 r m 220 f c 41 tr1 (al = 190 nh) d41 mur4100 52 turns 7 turns 1 v 100 v mur120 9 turns d42 f 470 m v 16 v 42 c 2 mur120 5 turns d43 8.5 v m v 470 43 c 3 f m 22 26 c f 1n4148 d26 13 7 9 r 35 w 15 c 9 220 pf m 7 150 c f/385 v 4.7 m w 10 r d1-d4 4 x 1n4007 1 nf c 10 rfi filter 180-270 v 3.15 a f1 tda 16846 ic1 14 1 77 turns d10 ba1 59 d11 t1 n6055 spp ( w 1.4 )
tda 16846 tda 16847 data sheet 26 2000-01-14 figure 17 circuit diagram for application with temporary high power circuit aes02738 25 c 10 nf 4 r 24 18 k w 11 1 nf 24 c 23 r 3.9 m w 1 m r w 22 680 pf 22 c 2 5 3 29 r w 9.1 k 2 k p 10 w 10, 12 c 22 150 pf 56 k r 30 w 1.5 nf 30 c 9 9.1 k w 38 r m 220 f c 41 tr1 (al = 190 nh) d41 mur4100 52 turns 7 turns 1 v 100 v mur120 9 turns d42 f 470 m v 16 v 42 c 2 mur120 5 turns d43 8.5 v m v 470 43 c 3 f m 22 26 c f 1n4148 13 r 35 w 15 c 9 220 pf m 7 150 c f/385 v 4.7 m w 10 r d1-d4 4 x 1n4007 1 nf c 10 rfi filter 180-270 v 3.15 a f1 tda 16847 ic1 14 1 77 turns d10 ba 159 d11 t1 n6055 spp ( w 1.4 ) d26 7 32 r 51 k w 33 r 1 m w c 31 100 pf c 32 4.7 m f 6 8
tda 16846 tda 16847 data sheet 27 2000-01-14 package outlines p-dip-14-3 (plastic dual in-line package) gpd05584 sorts of packing package outlines for tubes, trays etc. are contained in our data book "package information". dimensions in mm
tda 16846 tda 16847 data sheet 28 2000-01-14 p-dso-14-3 (plastic dual in-line package) sorts of packing package outlines for tubes, trays etc. are contained in our data book "package information". dimensions in mm

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